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@@ -0,0 +1,325 @@
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// Package vm implements the bytecode CPU that runs ship programs.
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//
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// The machine has 16 32-bit registers (r15 is the stack pointer), a program
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// ROM and a byte-addressable little-endian data RAM. Peripherals are reached
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// through IN/OUT port instructions. Every instruction is 4 bytes:
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//
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// byte 0: opcode | byte 1: ra<<4 | rb | bytes 2-3: signed 16-bit immediate
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//
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// Branch/jump immediates are offsets in instructions relative to the next
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// instruction. Each tick a CPU runs up to a cycle budget or until it executes
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// YIELD; state persists between ticks so an over-long computation simply
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// continues on the next tick.
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package vm
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import (
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"encoding/binary"
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"fmt"
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)
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type Op uint8
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const (
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NOP Op = iota
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YIELD
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HALT
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LDI
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LUI
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MOV
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ADD
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SUB
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MUL
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DIV
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MOD
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AND
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OR
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XOR
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SHL
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SHR
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SAR
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ADDI
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JMP
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BEQ
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BNE
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BLT
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BGE
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CALL
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RET
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PUSH
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POP
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LDB
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LDH
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LDW
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STB
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STH
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STW
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IN
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OUT
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numOps
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)
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const (
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NumRegs = 16
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SP = 15
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)
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type Status uint8
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const (
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Running Status = iota
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Yielded // finished this tick's work voluntarily
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Halted
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Faulted
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)
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func (s Status) String() string {
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return [...]string{"running", "yielded", "halted", "faulted"}[s]
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}
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// Bus connects the CPU to peripherals.
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type Bus interface {
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In(port uint16) int32
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Out(port uint16, v int32)
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}
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type CPU struct {
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R [NumRegs]int32
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PC uint32 // byte address into Prog
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Prog []byte
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RAM []byte
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Status Status
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Fault string
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}
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// New creates a CPU with the program loaded and the stack pointer at the top
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// of RAM.
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func New(prog []byte, ramBytes int) (*CPU, error) {
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if len(prog)%4 != 0 {
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return nil, fmt.Errorf("program length %d is not a multiple of 4", len(prog))
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}
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c := &CPU{Prog: append([]byte(nil), prog...), RAM: make([]byte, ramBytes)}
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c.R[SP] = int32(ramBytes)
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return c, nil
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}
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func (c *CPU) fault(format string, args ...any) {
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c.Status = Faulted
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c.Fault = fmt.Sprintf(format, args...)
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}
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func cost(op Op) int {
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switch op {
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case MUL:
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return 2
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case DIV, MOD:
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return 8
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}
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return 1
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}
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// Run executes instructions until the budget is spent, YIELD, HALT or a
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// fault, returning the cycles used. A yielded CPU resumes on the next call.
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func (c *CPU) Run(bus Bus, budget int) int {
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if c.Status == Halted || c.Status == Faulted {
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return 0
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}
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c.Status = Running
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used := 0
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for used < budget {
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if int(c.PC)+4 > len(c.Prog) {
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// Falling off the end of the program halts the CPU.
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c.Status = Halted
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break
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}
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w := binary.LittleEndian.Uint32(c.Prog[c.PC:])
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op := Op(w)
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ra, rb := (w>>12)&0xf, (w>>8)&0xf
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imm := int32(int16(w >> 16))
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if op >= numOps {
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c.fault("illegal opcode %d at pc=%d", op, c.PC)
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break
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}
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used += cost(op)
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next := c.PC + 4
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r := &c.R
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switch op {
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case NOP:
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case YIELD:
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c.Status = Yielded
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case HALT:
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c.Status = Halted
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case LDI:
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r[ra] = imm
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case LUI:
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r[ra] = int32(uint32(imm)<<16 | uint32(r[ra])&0xffff)
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case MOV:
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r[ra] = r[rb]
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case ADD:
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r[ra] += r[rb]
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case SUB:
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r[ra] -= r[rb]
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case MUL:
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r[ra] *= r[rb]
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case DIV, MOD:
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d := r[rb]
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if d == 0 {
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c.fault("division by zero at pc=%d", c.PC)
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break
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}
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switch {
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case d == -1: // avoid MinInt32 / -1 overflow panic semantics
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if op == DIV {
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r[ra] = -r[ra]
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} else {
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r[ra] = 0
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}
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case op == DIV:
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r[ra] /= d
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default:
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r[ra] %= d
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}
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case AND:
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r[ra] &= r[rb]
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case OR:
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r[ra] |= r[rb]
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case XOR:
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r[ra] ^= r[rb]
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case SHL:
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r[ra] = int32(uint32(r[ra]) << (uint32(r[rb]) & 31))
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case SHR:
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r[ra] = int32(uint32(r[ra]) >> (uint32(r[rb]) & 31))
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case SAR:
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r[ra] >>= uint32(r[rb]) & 31
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case ADDI:
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r[ra] += imm
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case JMP:
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next = uint32(int64(next) + int64(imm)*4)
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case BEQ, BNE, BLT, BGE:
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var t bool
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switch op {
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case BEQ:
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t = r[ra] == r[rb]
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case BNE:
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t = r[ra] != r[rb]
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case BLT:
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t = r[ra] < r[rb]
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case BGE:
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t = r[ra] >= r[rb]
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}
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if t {
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next = uint32(int64(next) + int64(imm)*4)
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}
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case CALL:
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if c.push(int32(next)) {
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next = uint32(int64(next) + int64(imm)*4)
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}
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case RET:
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if v, ok := c.pop(); ok {
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next = uint32(v)
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}
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case PUSH:
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c.push(r[ra])
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case POP:
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if v, ok := c.pop(); ok {
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r[ra] = v
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}
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case LDB, LDH, LDW:
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n := accessSize(op)
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if a, ok := c.addr(r[rb]+imm, n); ok {
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var v uint32
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for i := n - 1; i >= 0; i-- {
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v = v<<8 | uint32(c.RAM[a+i])
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}
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r[ra] = int32(v)
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}
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case STB, STH, STW:
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n := accessSize(op)
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if a, ok := c.addr(r[rb]+imm, n); ok {
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v := uint32(r[ra])
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for i := 0; i < n; i++ {
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c.RAM[a+i] = byte(v >> (8 * i))
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}
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}
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case IN:
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r[ra] = bus.In(uint16(imm))
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case OUT:
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bus.Out(uint16(imm), r[ra])
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}
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if c.Status == Faulted {
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break
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}
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c.PC = next
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if c.Status != Running {
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break
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}
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}
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return used
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}
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func accessSize(op Op) int {
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switch op {
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case LDB, STB:
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return 1
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case LDH, STH:
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return 2
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}
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return 4
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}
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func (c *CPU) addr(a int32, n int) (int, bool) {
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if a < 0 || int(a)+n > len(c.RAM) {
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c.fault("memory access out of range: %d", a)
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return 0, false
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}
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return int(a), true
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}
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func (c *CPU) push(v int32) bool {
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a, ok := c.addr(c.R[SP]-4, 4)
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if !ok {
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return false
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}
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c.R[SP] -= 4
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binary.LittleEndian.PutUint32(c.RAM[a:], uint32(v))
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return true
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}
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func (c *CPU) pop() (int32, bool) {
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a, ok := c.addr(c.R[SP], 4)
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if !ok {
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return 0, false
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}
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c.R[SP] += 4
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return int32(binary.LittleEndian.Uint32(c.RAM[a:])), true
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}
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// Encode builds one instruction word.
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func Encode(op Op, ra, rb int, imm int32) uint32 {
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return uint32(op) | uint32(rb&0xf)<<8 | uint32(ra&0xf)<<12 | uint32(uint16(imm))<<16
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}
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// MarshalState serialises the mutable CPU state (not the program).
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func (c *CPU) MarshalState() []byte {
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b := make([]byte, 0, NumRegs*4+8+len(c.RAM))
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for _, r := range c.R {
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b = binary.LittleEndian.AppendUint32(b, uint32(r))
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}
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b = binary.LittleEndian.AppendUint32(b, c.PC)
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b = append(b, byte(c.Status), 0, 0, 0)
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return append(b, c.RAM...)
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}
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// UnmarshalState restores state produced by MarshalState.
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func (c *CPU) UnmarshalState(b []byte) error {
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hdr := NumRegs*4 + 8
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if len(b) != hdr+len(c.RAM) {
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return fmt.Errorf("state size %d does not match expected %d", len(b), hdr+len(c.RAM))
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}
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for i := range c.R {
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c.R[i] = int32(binary.LittleEndian.Uint32(b[i*4:]))
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}
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c.PC = binary.LittleEndian.Uint32(b[NumRegs*4:])
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c.Status = Status(b[NumRegs*4+4])
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copy(c.RAM, b[hdr:])
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return nil
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}
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